{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11977828","patent":{"patent_number":"US-11977828","title":"Method for detecting stochastic weak points of layout pattern of semiconductor integrated circuit and computer system performing the same","assignee":null,"inventors":[],"filing_date":"2021-09-27T00:00:00.000Z","publication_date":"2024-05-07T00:00:00.000Z","cpc_codes":["G06F","H01L","G06F","G06F","G06F","H01L"],"num_claims":15,"abstract":"A method for detecting a stochastic weak point of a layout pattern of a semiconductor integrated circuit includes: forming a semiconductor integrated circuit by exposing a wafer which is masked by a layout pattern and coated with a photoresist to light, and etching the circuit according to the layout pattern, calculating line edge roughness (LER) of the circuit, and calculating a variability constant for fitting the line edge roughness to a normal distribution from a polymer concentration value of the photoresist. The polymer concentration value is calculated from modeling the layout pattern, a total value of intensity of light reaching the photoresist, and an intensity value of light reaching one point of the photoresist. The method further includes calculating a probability distribution of the polymer concentration value of the layout pattern based on the variability constant, and calculating a stochastic weak point of the layout pattern from the probability distribution."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for detecting stochastic weak points of layout pattern of semiconductor integrated circuit and computer system performing the same","description":"A method for detecting a stochastic weak point of a layout pattern of a semiconductor integrated circuit includes: forming a semiconductor integrated circuit by exposing a wafer which is masked by a l","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11977828","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11977828","citation_suggestion":"Patentable. \"Method for detecting stochastic weak points of layout pattern of semiconductor integrated circuit and computer system performing the same\" (US-11977828). https://patentable.app/patents/US-11977828","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11977828","json":"https://patentable.app/api/llm-context/US-11977828","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:07:07.550Z"}