{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11978634","patent":{"patent_number":"US-11978634","title":"Reduce well dopant loss in FinFETs through co-implantation","assignee":null,"inventors":[],"filing_date":"2022-05-25T00:00:00.000Z","publication_date":"2024-05-07T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reduce well dopant loss in FinFETs through co-implantation","description":"A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the s","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11978634","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11978634","citation_suggestion":"Patentable. \"Reduce well dopant loss in FinFETs through co-implantation\" (US-11978634). https://patentable.app/patents/US-11978634","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11978634","json":"https://patentable.app/api/llm-context/US-11978634","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T10:36:00.755Z"}