{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11983121","patent":{"patent_number":"US-11983121","title":"Cache memory device and method for implementing cache scheduling using same","assignee":null,"inventors":[],"filing_date":"2023-11-15T00:00:00.000Z","publication_date":"2024-05-14T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":16,"abstract":"Provided is a cache memory device including a command reception unit for packetizing each of read commands and write commands and classifying them as even or odd; a cache scheduler comprising a first reorder scheduling queue for receiving commands classified as even numbers from the command reception unit and scheduling the commands classified as even numbers for cache memory accesses and a second reorder scheduling queue for receiving commands classified as odd numbers from the command reception unit and scheduling the commands classified as odd numbers for cache memory accesses; and an access execution unit for performing cache memory accesses via a cache tag to scheduled commands classified as even numbers and scheduled commands classified as odd numbers."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cache memory device and method for implementing cache scheduling using same","description":"Provided is a cache memory device including a command reception unit for packetizing each of read commands and write commands and classifying them as even or odd; a cache scheduler comprising a first ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11983121","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11983121","citation_suggestion":"Patentable. \"Cache memory device and method for implementing cache scheduling using same\" (US-11983121). https://patentable.app/patents/US-11983121","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11983121","json":"https://patentable.app/api/llm-context/US-11983121","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:16:42.086Z"}