{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11983416","patent":{"patent_number":"US-11983416","title":"Base die, memory system, and semiconductor structure","assignee":null,"inventors":[],"filing_date":"2022-05-04T00:00:00.000Z","publication_date":"2024-05-14T00:00:00.000Z","cpc_codes":["G06F","G11C","G06F","G06F","G11C"],"num_claims":14,"abstract":"A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Base die, memory system, and semiconductor structure","description":"A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11983416","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11983416","citation_suggestion":"Patentable. \"Base die, memory system, and semiconductor structure\" (US-11983416). https://patentable.app/patents/US-11983416","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11983416","json":"https://patentable.app/api/llm-context/US-11983416","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:01:40.192Z"}