{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11984151","patent":{"patent_number":"US-11984151","title":"Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)","assignee":null,"inventors":[],"filing_date":"2022-06-27T00:00:00.000Z","publication_date":"2024-05-14T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":32,"abstract":"A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)","description":"A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11984151","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11984151","citation_suggestion":"Patentable. \"Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)\" (US-11984151). https://patentable.app/patents/US-11984151","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11984151","json":"https://patentable.app/api/llm-context/US-11984151","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T08:25:27.832Z"}