{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11984171","patent":{"patent_number":"US-11984171","title":"Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices","assignee":null,"inventors":[],"filing_date":"2022-06-15T00:00:00.000Z","publication_date":"2024-05-14T00:00:00.000Z","cpc_codes":["G11C","G11C","G06F","G11C","G11C"],"num_claims":20,"abstract":"A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices","description":"A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in respon","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11984171","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11984171","citation_suggestion":"Patentable. \"Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices\" (US-11984171). https://patentable.app/patents/US-11984171","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11984171","json":"https://patentable.app/api/llm-context/US-11984171","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T16:15:00.635Z"}