{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11984186","patent":{"patent_number":"US-11984186","title":"Apparatuses and methods for repairing defective memory cells based on a specified error rate for certain memory cells","assignee":null,"inventors":[],"filing_date":"2021-11-10T00:00:00.000Z","publication_date":"2024-05-14T00:00:00.000Z","cpc_codes":["G06F","G11C","G06F","G06F","G06F","G06F","G06F","G06F","G11C","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","H04L"],"num_claims":17,"abstract":"Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatuses and methods for repairing defective memory cells based on a specified error rate for certain memory cells","description":"Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11984186","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11984186","citation_suggestion":"Patentable. \"Apparatuses and methods for repairing defective memory cells based on a specified error rate for certain memory cells\" (US-11984186). https://patentable.app/patents/US-11984186","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11984186","json":"https://patentable.app/api/llm-context/US-11984186","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T18:35:40.858Z"}