{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11984193","patent":{"patent_number":"US-11984193","title":"Page buffer circuits in three-dimensional memory devices","assignee":null,"inventors":[],"filing_date":"2022-03-04T00:00:00.000Z","publication_date":"2024-05-14T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Page buffer circuits in three-dimensional memory devices","description":"The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line se","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11984193","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11984193","citation_suggestion":"Patentable. \"Page buffer circuits in three-dimensional memory devices\" (US-11984193). https://patentable.app/patents/US-11984193","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11984193","json":"https://patentable.app/api/llm-context/US-11984193","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:15:43.248Z"}