{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11984194","patent":{"patent_number":"US-11984194","title":"Layout of delay circuit unit, layout of delay circuit, and semiconductor memory","assignee":null,"inventors":[],"filing_date":"2022-04-25T00:00:00.000Z","publication_date":"2024-05-14T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C"],"num_claims":18,"abstract":"A layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory are provided. The layout of the delay circuit unit includes multiple layout units arranged in an array and each forming a NOT-AND (NAND) gate circuit; here several layout units conforming to a first layout pattern are sequentially arranged in a first row of the array; and several layout units conforming to a second layout pattern are sequentially arranged in a second row of the array; here the first layout pattern is different from the second layout pattern, and the first layout pattern and the second layout pattern are such that the first row and the second row form a center-symmetrical structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Layout of delay circuit unit, layout of delay circuit, and semiconductor memory","description":"A layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory are provided. The layout of the delay circuit unit includes multiple layout units arranged in an array and eac","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11984194","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11984194","citation_suggestion":"Patentable. \"Layout of delay circuit unit, layout of delay circuit, and semiconductor memory\" (US-11984194). https://patentable.app/patents/US-11984194","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11984194","json":"https://patentable.app/api/llm-context/US-11984194","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T16:14:43.681Z"}