{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11990405","patent":{"patent_number":"US-11990405","title":"Semiconductor arrangement and method for producing a semiconductor arrangement","assignee":null,"inventors":[],"filing_date":"2022-03-25T00:00:00.000Z","publication_date":"2024-05-21T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":6,"abstract":"A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor arrangement and method for producing a semiconductor arrangement","description":"A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an up","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11990405","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11990405","citation_suggestion":"Patentable. \"Semiconductor arrangement and method for producing a semiconductor arrangement\" (US-11990405). https://patentable.app/patents/US-11990405","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11990405","json":"https://patentable.app/api/llm-context/US-11990405","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T11:54:04.558Z"}