{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11991458","patent":{"patent_number":"US-11991458","title":"Column arithmetic logic unit design for dual conversion gain sensor supporting correlated multiple sampling and three readout phase detection autofocus","assignee":null,"inventors":[],"filing_date":"2022-09-21T00:00:00.000Z","publication_date":"2024-05-21T00:00:00.000Z","cpc_codes":["H04N","H04N","H04N"],"num_claims":29,"abstract":"An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Column arithmetic logic unit design for dual conversion gain sensor supporting correlated multiple sampling and three readout phase detection autofocus","description":"An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outpu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11991458","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11991458","citation_suggestion":"Patentable. \"Column arithmetic logic unit design for dual conversion gain sensor supporting correlated multiple sampling and three readout phase detection autofocus\" (US-11991458). https://patentable.app/patents/US-11991458","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11991458","json":"https://patentable.app/api/llm-context/US-11991458","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:51:45.723Z"}