{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11994936","patent":{"patent_number":"US-11994936","title":"Automated optimization of error-handling flows in memory devices","assignee":null,"inventors":[],"filing_date":"2022-08-29T00:00:00.000Z","publication_date":"2024-05-28T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Automated optimization of error-handling flows in memory devices","description":"Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a f","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11994936","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11994936","citation_suggestion":"Patentable. \"Automated optimization of error-handling flows in memory devices\" (US-11994936). https://patentable.app/patents/US-11994936","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11994936","json":"https://patentable.app/api/llm-context/US-11994936","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T12:22:40.123Z"}