{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11995323","patent":{"patent_number":"US-11995323","title":"Memory controller and operating method thereof","assignee":null,"inventors":[],"filing_date":"2022-11-10T00:00:00.000Z","publication_date":"2024-05-28T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":33,"abstract":"A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M−1” and second data corresponding to a write sequence index “M+1”; a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory controller and operating method thereof","description":"A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence index","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11995323","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11995323","citation_suggestion":"Patentable. \"Memory controller and operating method thereof\" (US-11995323). https://patentable.app/patents/US-11995323","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11995323","json":"https://patentable.app/api/llm-context/US-11995323","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T01:51:03.306Z"}