{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11996136","patent":{"patent_number":"US-11996136","title":"Semiconductor-element-including memory device","assignee":null,"inventors":[],"filing_date":"2023-08-14T00:00:00.000Z","publication_date":"2024-05-28T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":6,"abstract":"A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor-element-including memory device","description":"A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11996136","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11996136","citation_suggestion":"Patentable. \"Semiconductor-element-including memory device\" (US-11996136). https://patentable.app/patents/US-11996136","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11996136","json":"https://patentable.app/api/llm-context/US-11996136","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T13:14:09.310Z"}