{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-11996165","patent":{"patent_number":"US-11996165","title":"Memory chip and operating method thereof","assignee":null,"inventors":[],"filing_date":"2022-05-17T00:00:00.000Z","publication_date":"2024-05-28T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":11,"abstract":"A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory chip and operating method thereof","description":"A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-11996165","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-11996165","citation_suggestion":"Patentable. \"Memory chip and operating method thereof\" (US-11996165). https://patentable.app/patents/US-11996165","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-11996165","json":"https://patentable.app/api/llm-context/US-11996165","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T15:08:57.630Z"}