{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12001336","patent":{"patent_number":"US-12001336","title":"Hybrid parallel programming of single-level cell memory","assignee":null,"inventors":[],"filing_date":"2022-01-26T00:00:00.000Z","publication_date":"2024-06-04T00:00:00.000Z","cpc_codes":["G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G06F"],"num_claims":20,"abstract":"A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Hybrid parallel programming of single-level cell memory","description":"A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12001336","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12001336","citation_suggestion":"Patentable. \"Hybrid parallel programming of single-level cell memory\" (US-12001336). https://patentable.app/patents/US-12001336","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12001336","json":"https://patentable.app/api/llm-context/US-12001336","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:45:14.505Z"}