{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12001386","patent":{"patent_number":"US-12001386","title":"Disabling processor cores for best latency in a multiple core processor","assignee":null,"inventors":[],"filing_date":"2022-07-22T00:00:00.000Z","publication_date":"2024-06-04T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":17,"abstract":"An information handling system includes a model-specific register and a basic input/output system (BIOS). The BIOS receives a selection of a number of processor cores to have enabled in a multiple core processor. In response to the reception of the selection of the number of processor cores to have enabled, the BIOS calculates a different latency for each of a plurality of processor cores in the multiple core processor. Based on the calculated different latency for each of the processor cores, the BIOS determines a first subset of the processor cores to enable and a second subset of the processor cores to disable. The BIOS sets bits in the model-specific register to indicate that the first subset of the processor cores is enabled and the second subset of the processor cores is disabled."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Disabling processor cores for best latency in a multiple core processor","description":"An information handling system includes a model-specific register and a basic input/output system (BIOS). The BIOS receives a selection of a number of processor cores to have enabled in a multiple cor","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12001386","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12001386","citation_suggestion":"Patentable. \"Disabling processor cores for best latency in a multiple core processor\" (US-12001386). https://patentable.app/patents/US-12001386","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12001386","json":"https://patentable.app/api/llm-context/US-12001386","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T16:14:31.535Z"}