{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12002515","patent":{"patent_number":"US-12002515","title":"Memory device configured to apply different erase intensities to different blocks during an erase operation and memory system for instructing the memory device to carry out the erase operation","assignee":null,"inventors":[],"filing_date":"2022-03-03T00:00:00.000Z","publication_date":"2024-06-04T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device configured to apply different erase intensities to different blocks during an erase operation and memory system for instructing the memory device to carry out the erase operation","description":"A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line conn","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12002515","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12002515","citation_suggestion":"Patentable. \"Memory device configured to apply different erase intensities to different blocks during an erase operation and memory system for instructing the memory device to carry out the erase operation\" (US-12002515). https://patentable.app/patents/US-12002515","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12002515","json":"https://patentable.app/api/llm-context/US-12002515","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T18:03:48.586Z"}