{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12002767","patent":{"patent_number":"US-12002767","title":"Integrated circuit package and method","assignee":null,"inventors":[],"filing_date":"2022-01-03T00:00:00.000Z","publication_date":"2024-06-04T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 μm to 30 μm; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integrated circuit package and method","description":"In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redist","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12002767","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12002767","citation_suggestion":"Patentable. \"Integrated circuit package and method\" (US-12002767). https://patentable.app/patents/US-12002767","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12002767","json":"https://patentable.app/api/llm-context/US-12002767","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:22:30.320Z"}