{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12002770","patent":{"patent_number":"US-12002770","title":"Power management semiconductor package and manufacturing method thereof","assignee":null,"inventors":[],"filing_date":"2020-02-11T00:00:00.000Z","publication_date":"2024-06-04T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A package includes first and second redistribution structures, a die, a permalloy structure, a molding material and a plurality of through vias. The first redistribution structure includes a first metal pattern. The die is disposed over the first redistribution structure. The molding material is disposed over the first redistribution structure and surrounds the die and the permalloy structure. The second redistribution structure is disposed over the die, the permalloy structure and the molding material, and includes a second metal pattern. The through vias penetrate the molding material and connects the first metal pattern to the second metal pattern. The permalloy structure includes a first member and a second member isolated from the first member, the first member and the second member are surrounded by the plurality of through vias and sandwiched between the first metal pattern and the second metal pattern. A method for forming a package is also provided."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power management semiconductor package and manufacturing method thereof","description":"A package includes first and second redistribution structures, a die, a permalloy structure, a molding material and a plurality of through vias. The first redistribution structure includes a first met","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12002770","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12002770","citation_suggestion":"Patentable. \"Power management semiconductor package and manufacturing method thereof\" (US-12002770). https://patentable.app/patents/US-12002770","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12002770","json":"https://patentable.app/api/llm-context/US-12002770","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T03:14:56.493Z"}