{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12004354","patent":{"patent_number":"US-12004354","title":"Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor","assignee":null,"inventors":[],"filing_date":"2021-04-20T00:00:00.000Z","publication_date":"2024-06-04T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":7,"abstract":"A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor","description":"A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regio","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12004354","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12004354","citation_suggestion":"Patentable. \"Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor\" (US-12004354). https://patentable.app/patents/US-12004354","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12004354","json":"https://patentable.app/api/llm-context/US-12004354","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T06:07:16.506Z"}