{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12007823","patent":{"patent_number":"US-12007823","title":"Power management of a processor and a platform in active state and low power state","assignee":null,"inventors":[],"filing_date":"2022-03-23T00:00:00.000Z","publication_date":"2024-06-11T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":19,"abstract":"A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power management of a processor and a platform in active state and low power state","description":"A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual pr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12007823","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12007823","citation_suggestion":"Patentable. \"Power management of a processor and a platform in active state and low power state\" (US-12007823). https://patentable.app/patents/US-12007823","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12007823","json":"https://patentable.app/api/llm-context/US-12007823","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:21:32.224Z"}