{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-12009260","patent":{"patent_number":"US-12009260","title":"Method and system of forming integrated circuit","assignee":null,"inventors":[],"filing_date":"2020-09-03T00:00:00.000Z","publication_date":"2024-06-11T00:00:00.000Z","cpc_codes":["G06F","H01L","H01L","H01L","G06F"],"num_claims":20,"abstract":"A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system of forming integrated circuit","description":"A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full p","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-12009260","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-12009260","citation_suggestion":"Patentable. \"Method and system of forming integrated circuit\" (US-12009260). https://patentable.app/patents/US-12009260","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-12009260","json":"https://patentable.app/api/llm-context/US-12009260","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T16:14:43.664Z"}