{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8461040","patent":{"patent_number":"US-8461040","title":"Method of forming shielded gate power transistor utilizing chemical mechanical planarization","assignee":null,"inventors":[],"filing_date":"2011-03-07T00:00:00.000Z","publication_date":"2013-06-11T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":14,"abstract":"A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of forming shielded gate power transistor utilizing chemical mechanical planarization","description":"A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches wit","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8461040","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8461040","citation_suggestion":"Patentable. \"Method of forming shielded gate power transistor utilizing chemical mechanical planarization\" (US-8461040). https://patentable.app/patents/US-8461040","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8461040","json":"https://patentable.app/api/llm-context/US-8461040","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:35:03.557Z"}