{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8462562","patent":{"patent_number":"US-8462562","title":"Memory device with area efficient power gating circuitry","assignee":null,"inventors":[],"filing_date":"2011-11-18T00:00:00.000Z","publication_date":"2013-06-11T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory device with area efficient power gating circuitry","description":"A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8462562","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8462562","citation_suggestion":"Patentable. \"Memory device with area efficient power gating circuitry\" (US-8462562). https://patentable.app/patents/US-8462562","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8462562","json":"https://patentable.app/api/llm-context/US-8462562","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:38:22.063Z"}