{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8462571","patent":{"patent_number":"US-8462571","title":"DRAM and method for testing the same in the wafer level burn-in test mode","assignee":null,"inventors":[],"filing_date":"2011-07-19T00:00:00.000Z","publication_date":"2013-06-11T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":9,"abstract":"A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"DRAM and method for testing the same in the wafer level burn-in test mode","description":"A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8462571","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8462571","citation_suggestion":"Patentable. \"DRAM and method for testing the same in the wafer level burn-in test mode\" (US-8462571). https://patentable.app/patents/US-8462571","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8462571","json":"https://patentable.app/api/llm-context/US-8462571","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T03:23:45.077Z"}