{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8463836","patent":{"patent_number":"US-8463836","title":"Performing mathematical and logical operations in multiple sub-cycles","assignee":null,"inventors":[],"filing_date":"2005-11-07T00:00:00.000Z","publication_date":"2013-06-11T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":30,"abstract":"Some embodiments provide a reconfigurable IC. This IC includes a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle. To perform the mathematical operation when at least one operand has n bits, the reconfigurable circuits performs a first sub-operation on m of n bits in a first reconfiguration cycle, and a second sub-operation on p of n bits in a second reconfiguration cycle. The reconfigurable IC also includes at least one storage element for storing at least a portion of the results of the first sub-operation for use during the second reconfiguration cycle in the second sub-operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Performing mathematical and logical operations in multiple sub-cycles","description":"Some embodiments provide a reconfigurable IC. This IC includes a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle. To perform the mathemati","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8463836","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8463836","citation_suggestion":"Patentable. \"Performing mathematical and logical operations in multiple sub-cycles\" (US-8463836). https://patentable.app/patents/US-8463836","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8463836","json":"https://patentable.app/api/llm-context/US-8463836","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:05:30.250Z"}