{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8466060","patent":{"patent_number":"US-8466060","title":"Stackable power MOSFET, power MOSFET stack, and process of manufacture","assignee":null,"inventors":[],"filing_date":"2010-04-30T00:00:00.000Z","publication_date":"2013-06-18T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":24,"abstract":"A thin and stackable power MOSFET (SP-MOSFET) and method are proposed. The SVP-MOSFET includes semiconductor substrate with bottom drain metal layer. Formed atop the semiconductor substrate are trenched gate regions and source-body regions. A patterned gate metal layer and source-body metal layer respectively contact trenched gate regions and source-body regions. At least one of through substrate drain via (TSDV), through substrate gate via (TSGV), through substrate source via (TSSV) is provided. The TSDV, formed through semiconductor substrate and in contact with drain metal layer, has top drain contacting pad and bottom drain contacting pad for making top and bottom contacts thereto. Similarly the TSGV, formed through semiconductor substrate and in contact with gate metal layer, has top gate contacting pad and bottom gate contacting pad. Likewise the TSSV, formed through semiconductor substrate and in contact with source-body metal layer, has top source contacting pad and bottom source contacting pad."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stackable power MOSFET, power MOSFET stack, and process of manufacture","description":"A thin and stackable power MOSFET (SP-MOSFET) and method are proposed. The SVP-MOSFET includes semiconductor substrate with bottom drain metal layer. Formed atop the semiconductor substrate are trench","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8466060","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8466060","citation_suggestion":"Patentable. \"Stackable power MOSFET, power MOSFET stack, and process of manufacture\" (US-8466060). https://patentable.app/patents/US-8466060","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8466060","json":"https://patentable.app/api/llm-context/US-8466060","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T08:38:08.072Z"}