{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8466501","patent":{"patent_number":"US-8466501","title":"Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET","assignee":null,"inventors":[],"filing_date":"2010-05-21T00:00:00.000Z","publication_date":"2013-06-18T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":19,"abstract":"An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap)."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET","description":"An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the ch","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8466501","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8466501","citation_suggestion":"Patentable. \"Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET\" (US-8466501). https://patentable.app/patents/US-8466501","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8466501","json":"https://patentable.app/api/llm-context/US-8466501","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T19:07:37.555Z"}