{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8467233","patent":{"patent_number":"US-8467233","title":"Asymmetric static random access memory cell with dual stress liner","assignee":null,"inventors":[],"filing_date":"2011-06-06T00:00:00.000Z","publication_date":"2013-06-18T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":16,"abstract":"A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Asymmetric static random access memory cell with dual stress liner","description":"A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Asymmetry is incorporated","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8467233","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8467233","citation_suggestion":"Patentable. \"Asymmetric static random access memory cell with dual stress liner\" (US-8467233). https://patentable.app/patents/US-8467233","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8467233","json":"https://patentable.app/api/llm-context/US-8467233","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:56:42.903Z"}