{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8468294","patent":{"patent_number":"US-8468294","title":"Non-volatile memory with multi-gear control using on-chip folding of data","assignee":null,"inventors":[],"filing_date":"2009-12-18T00:00:00.000Z","publication_date":"2013-06-18T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G06F","G06F","G11C","G11C","G11C"],"num_claims":18,"abstract":"A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Non-volatile memory with multi-gear control using on-chip folding of data","description":"A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8468294","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8468294","citation_suggestion":"Patentable. \"Non-volatile memory with multi-gear control using on-chip folding of data\" (US-8468294). https://patentable.app/patents/US-8468294","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8468294","json":"https://patentable.app/api/llm-context/US-8468294","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T21:55:41.095Z"}