{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8468407","patent":{"patent_number":"US-8468407","title":"Method for creating test clock domain during integrated circuit design, and associated computer readable medium","assignee":null,"inventors":[],"filing_date":"2011-08-19T00:00:00.000Z","publication_date":"2013-06-18T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":17,"abstract":"In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for creating test clock domain during integrated circuit design, and associated computer readable medium","description":"In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, th","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8468407","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8468407","citation_suggestion":"Patentable. \"Method for creating test clock domain during integrated circuit design, and associated computer readable medium\" (US-8468407). https://patentable.app/patents/US-8468407","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8468407","json":"https://patentable.app/api/llm-context/US-8468407","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:15:04.475Z"}