{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8468482","patent":{"patent_number":"US-8468482","title":"Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits","assignee":null,"inventors":[],"filing_date":"2011-03-14T00:00:00.000Z","publication_date":"2013-06-18T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":18,"abstract":"A technique models and simulates the impact of imperfectly patterned via arrays on integrated circuits through the use of hierarchical models and a hierarchical circuit simulator. Through the hierarchical modeling and simulation approach discussed here, far more accurate electrical simulation and verification of networks is enabled for; performance, yield, and reliability. The approach further enables simulation of the effects of via process variations on large-scale circuit response. In an implementation, each via in a layout or in a via array is modeled as having an independent size from other vias based upon calibrated process simulation. The electrical characteristics of independent vias and via arrays are modeled and compiled into a reusable hierarchical distributed resistance via model. Hierarchical simulation is performed using these hierarchical distributed via models and enables more accurate results than traditional approaches."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits","description":"A technique models and simulates the impact of imperfectly patterned via arrays on integrated circuits through the use of hierarchical models and a hierarchical circuit simulator. Through the hierarch","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8468482","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8468482","citation_suggestion":"Patentable. \"Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits\" (US-8468482). https://patentable.app/patents/US-8468482","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8468482","json":"https://patentable.app/api/llm-context/US-8468482","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T11:05:31.248Z"}