{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8471597","patent":{"patent_number":"US-8471597","title":"Power saving circuit using a clock buffer and multiple flip-flops","assignee":null,"inventors":[],"filing_date":"2009-05-07T00:00:00.000Z","publication_date":"2013-06-25T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":13,"abstract":"A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Power saving circuit using a clock buffer and multiple flip-flops","description":"A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a firs","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8471597","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8471597","citation_suggestion":"Patentable. \"Power saving circuit using a clock buffer and multiple flip-flops\" (US-8471597). https://patentable.app/patents/US-8471597","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8471597","json":"https://patentable.app/api/llm-context/US-8471597","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:46:32.996Z"}