{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8472265","patent":{"patent_number":"US-8472265","title":"Repairing circuit for memory circuit and method thereof and memory circuit using the same","assignee":null,"inventors":[],"filing_date":"2011-05-10T00:00:00.000Z","publication_date":"2013-06-25T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Repairing circuit for memory circuit and method thereof and memory circuit using the same","description":"A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during t","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8472265","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8472265","citation_suggestion":"Patentable. \"Repairing circuit for memory circuit and method thereof and memory circuit using the same\" (US-8472265). https://patentable.app/patents/US-8472265","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8472265","json":"https://patentable.app/api/llm-context/US-8472265","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T07:45:35.472Z"}