{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8472277","patent":{"patent_number":"US-8472277","title":"System and method for memory array decoding","assignee":null,"inventors":[],"filing_date":"2012-06-19T00:00:00.000Z","publication_date":"2013-06-25T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A memory system includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells, and a read/write module. The bit lines include a first bit line and a second bit line. The word lines include a first word line and a second word line. Each memory cell is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of the first bit line and the first word line. The second memory cell is located at the intersection of the second bit line and the second word line. The read/write module is configured to concurrently activate the first memory cell and the second memory cell for (i) a read operation or (ii) a write operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for memory array decoding","description":"A memory system includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells, and a read/write module. The bit lines include a first bit line and a second bit line. The wo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8472277","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8472277","citation_suggestion":"Patentable. \"System and method for memory array decoding\" (US-8472277). https://patentable.app/patents/US-8472277","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8472277","json":"https://patentable.app/api/llm-context/US-8472277","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:56:55.575Z"}