{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8473640","patent":{"patent_number":"US-8473640","title":"System and method for implementing a single chip having a multiple sub-layer PHY","assignee":null,"inventors":[],"filing_date":"2012-06-06T00:00:00.000Z","publication_date":"2013-06-25T00:00:00.000Z","cpc_codes":["H04B","H04L","H04L"],"num_claims":20,"abstract":"A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"System and method for implementing a single chip having a multiple sub-layer PHY","description":"A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver mod","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8473640","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8473640","citation_suggestion":"Patentable. \"System and method for implementing a single chip having a multiple sub-layer PHY\" (US-8473640). https://patentable.app/patents/US-8473640","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8473640","json":"https://patentable.app/api/llm-context/US-8473640","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:35:36.249Z"}