{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8473685","patent":{"patent_number":"US-8473685","title":"Cache memory device, processor, and control method for cache memory device to reduce power unnecessarily consumed by cache memory","assignee":null,"inventors":[],"filing_date":"2010-06-30T00:00:00.000Z","publication_date":"2013-06-25T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":18,"abstract":"A cache memory device that is connectable to an instruction controlling unit for outputting a memory access request and a storage device. The cache memory device includes a data memory unit, a tag memory unit for holding status information of data, a search unit for searching for a cache line of the tag memory unit, a comparison unit, and a controlling unit. The controlling unit, when the comparison unit detects a cache miss, stops the supply of a clock to the data memory unit, if the cache line storing the data requested at the storage device is not present in the data memory unit, according to the status information."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cache memory device, processor, and control method for cache memory device to reduce power unnecessarily consumed by cache memory","description":"A cache memory device that is connectable to an instruction controlling unit for outputting a memory access request and a storage device. The cache memory device includes a data memory unit, a tag mem","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8473685","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8473685","citation_suggestion":"Patentable. \"Cache memory device, processor, and control method for cache memory device to reduce power unnecessarily consumed by cache memory\" (US-8473685). https://patentable.app/patents/US-8473685","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8473685","json":"https://patentable.app/api/llm-context/US-8473685","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:05:27.538Z"}