{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8473706","patent":{"patent_number":"US-8473706","title":"Data processing circuit with multiplexed memory","assignee":null,"inventors":[],"filing_date":"2012-05-28T00:00:00.000Z","publication_date":"2013-06-25T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Data processing circuit with multiplexed memory","description":"A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8473706","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8473706","citation_suggestion":"Patentable. \"Data processing circuit with multiplexed memory\" (US-8473706). https://patentable.app/patents/US-8473706","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8473706","json":"https://patentable.app/api/llm-context/US-8473706","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:30:37.883Z"}