{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8473812","patent":{"patent_number":"US-8473812","title":"Method and system for error correction in flash memory","assignee":null,"inventors":[],"filing_date":"2010-11-15T00:00:00.000Z","publication_date":"2013-06-25T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G06F","G11C","G11C","G11C","G11C","G11C"],"num_claims":18,"abstract":"A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate a series of encoded data bits, and converts the series of encoded data bits into a series of data symbols. The controller sends, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array. The controller generates an output signal based on data associated with the stored series of data symbols. The output signal is characterized by a second number of digital levels greater than the first number of digital levels. The controller outputs a series of output data symbols based on the output signal."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for error correction in flash memory","description":"A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8473812","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8473812","citation_suggestion":"Patentable. \"Method and system for error correction in flash memory\" (US-8473812). https://patentable.app/patents/US-8473812","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8473812","json":"https://patentable.app/api/llm-context/US-8473812","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T05:38:39.887Z"}