{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8476116","patent":{"patent_number":"US-8476116","title":"Reduction of etch microloading for through silicon vias","assignee":null,"inventors":[],"filing_date":"2012-10-31T00:00:00.000Z","publication_date":"2013-07-02T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reduction of etch microloading for through silicon vias","description":"A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8476116","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8476116","citation_suggestion":"Patentable. \"Reduction of etch microloading for through silicon vias\" (US-8476116). https://patentable.app/patents/US-8476116","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8476116","json":"https://patentable.app/api/llm-context/US-8476116","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:23:04.193Z"}