{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8476146","patent":{"patent_number":"US-8476146","title":"Reducing wafer distortion through a low CTE layer","assignee":null,"inventors":[],"filing_date":"2010-12-03T00:00:00.000Z","publication_date":"2013-07-02T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":20,"abstract":"Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reducing wafer distortion through a low CTE layer","description":"Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the f","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8476146","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8476146","citation_suggestion":"Patentable. \"Reducing wafer distortion through a low CTE layer\" (US-8476146). https://patentable.app/patents/US-8476146","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8476146","json":"https://patentable.app/api/llm-context/US-8476146","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:59:46.654Z"}