{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8476630","patent":{"patent_number":"US-8476630","title":"Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon","assignee":null,"inventors":[],"filing_date":"2011-12-08T00:00:00.000Z","publication_date":"2013-07-02T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":12,"abstract":"A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon","description":"A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8476630","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8476630","citation_suggestion":"Patentable. \"Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon\" (US-8476630). https://patentable.app/patents/US-8476630","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8476630","json":"https://patentable.app/api/llm-context/US-8476630","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:21:23.490Z"}