{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8477833","patent":{"patent_number":"US-8477833","title":"Circuits and methods for DFE with reduced area and power consumption","assignee":null,"inventors":[],"filing_date":"2009-02-06T00:00:00.000Z","publication_date":"2013-07-02T00:00:00.000Z","cpc_codes":["H04L","H04L","H04L","H04L","H04L"],"num_claims":11,"abstract":"A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Circuits and methods for DFE with reduced area and power consumption","description":"A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch conf","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8477833","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8477833","citation_suggestion":"Patentable. \"Circuits and methods for DFE with reduced area and power consumption\" (US-8477833). https://patentable.app/patents/US-8477833","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8477833","json":"https://patentable.app/api/llm-context/US-8477833","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T05:14:14.161Z"}