{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8479085","patent":{"patent_number":"US-8479085","title":"Memory system with error correction decoder architecture having reduced latency and increased throughput","assignee":null,"inventors":[],"filing_date":"2008-08-14T00:00:00.000Z","publication_date":"2013-07-02T00:00:00.000Z","cpc_codes":["G06F","G11C","G11C"],"num_claims":20,"abstract":"A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory system with error correction decoder architecture having reduced latency and increased throughput","description":"A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a firs","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8479085","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8479085","citation_suggestion":"Patentable. \"Memory system with error correction decoder architecture having reduced latency and increased throughput\" (US-8479085). https://patentable.app/patents/US-8479085","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8479085","json":"https://patentable.app/api/llm-context/US-8479085","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:48:22.437Z"}