{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8482047","patent":{"patent_number":"US-8482047","title":"DRAM layout with vertical FETS and method of formation","assignee":null,"inventors":[],"filing_date":"2012-09-10T00:00:00.000Z","publication_date":"2013-07-09T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":19,"abstract":"DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"DRAM layout with vertical FETS and method of formation","description":"DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8482047","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8482047","citation_suggestion":"Patentable. \"DRAM layout with vertical FETS and method of formation\" (US-8482047). https://patentable.app/patents/US-8482047","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8482047","json":"https://patentable.app/api/llm-context/US-8482047","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:12:19.590Z"}