{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8482070","patent":{"patent_number":"US-8482070","title":"Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same","assignee":null,"inventors":[],"filing_date":"2012-08-01T00:00:00.000Z","publication_date":"2013-07-09T00:00:00.000Z","cpc_codes":["H01L"],"num_claims":10,"abstract":"An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same","description":"An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMO","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8482070","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8482070","citation_suggestion":"Patentable. \"Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same\" (US-8482070). https://patentable.app/patents/US-8482070","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8482070","json":"https://patentable.app/api/llm-context/US-8482070","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:31:06.658Z"}