{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8482105","patent":{"patent_number":"US-8482105","title":"Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same","assignee":null,"inventors":[],"filing_date":"2010-01-29T00:00:00.000Z","publication_date":"2013-07-09T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":9,"abstract":"A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same","description":"A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8482105","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8482105","citation_suggestion":"Patentable. \"Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same\" (US-8482105). https://patentable.app/patents/US-8482105","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8482105","json":"https://patentable.app/api/llm-context/US-8482105","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:31:03.215Z"}