{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8482977","patent":{"patent_number":"US-8482977","title":"Multi-bit cell memory devices using error correction coding and methods of operating the same","assignee":null,"inventors":[],"filing_date":"2011-03-02T00:00:00.000Z","publication_date":"2013-07-09T00:00:00.000Z","cpc_codes":["G11C","G06F"],"num_claims":20,"abstract":"A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Multi-bit cell memory devices using error correction coding and methods of operating the same","description":"A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8482977","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8482977","citation_suggestion":"Patentable. \"Multi-bit cell memory devices using error correction coding and methods of operating the same\" (US-8482977). https://patentable.app/patents/US-8482977","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8482977","json":"https://patentable.app/api/llm-context/US-8482977","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:33:34.684Z"}