{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8484007","patent":{"patent_number":"US-8484007","title":"Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model","assignee":null,"inventors":[],"filing_date":"2008-02-16T00:00:00.000Z","publication_date":"2013-07-09T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model","description":"A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8484007","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8484007","citation_suggestion":"Patentable. \"Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model\" (US-8484007). https://patentable.app/patents/US-8484007","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8484007","json":"https://patentable.app/api/llm-context/US-8484007","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:30:47.511Z"}